3rd-gen-core-family-mobile-vol-2-datasheet, ASK

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Mobile 3rd Generation Intel
®
Core™
Processor Family
Datasheet – Volume 2 of 2
June 2012
Document Number: 326769-002
 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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& configuration. For more information, visit
http://www.intel.com/technology/platform-technology/intel-amt
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a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code
Modules and an Intel TXT-compatible measured launched environment (MLE). Intel TXT also requires the system to contain a TPM
v1.s. For more information, visit
http://www.intel.com/technology/security
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
(VMM). Functionality, performance or other benefits will vary depending on hardware and software configurations. Software
applications may not be compatible with all operating systems. Consult your PC manufacturer. For more information, visit
http://www.intel.com/go/virtualization
Warning: Altering clock frequency and/or voltage may (i) reduce system stability and useful life of the system and processor; (ii)
cause the processor and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat
or other damage; and (v) affect system data integrity. Intel has not tested, and does not warranty, the operation of the processor
beyond its specifications.
Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-
enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For
more information including details on which processors support HT Technology, see
htp://www.intel.com/info/hyperthreading
.
“Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost
Technology performance varies depending on hardware, software and overall system configuration. Check with your PC
manufacturer on whether your system delivers Intel Turbo Boost Technology.For more information, see
http://www.intel.com/technology/turboboost
.”
Enhanced Intel SpeedStep
®
Technology See the
Processor Spec Finder
or contact your Intel repres
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device
drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software
configurations. Consult with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Enhanced Intel SpeedStep® Technology: See the Processor Spec Finder at http://ark.intel.com or contact your Intel
representative for more information.
All products, platforms, dates, and figures specified are preliminary based on current expectations, and are subject to change
without notice. All dates specified are target dates, are provided for planning purposes only and are subject to change.
Intel, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2012, Intel Corporation. All rights reserved.
2
Datasheet, Volume 2
Contents
1I tr cti
............................................................................................................ 13
2
Processor Configuration Registers
........................................................................... 15
2.1
Register Terminology ......................................................................................... 15
2.2
PCI Devices and Functions.................................................................................. 16
2.3
System Address Map ......................................................................................... 17
2.3.1
Legacy Address Range ......................................................................... 19
2.3.1.1
DOS Range (0h–9_FFFFh) .......................................................... 20
2.3.1.2
Legacy Video Area (A_0000h–B_FFFFh) ....................................... 20
2.3.1.3
PAM (C_0000h–F_FFFFh) ........................................................... 21
2.3.2
Main Memory Address Range (1 MB – TOLUD)......................................... 22
2.3.2.1
ISA Hole (15 MB – 16 MB) ......................................................... 22
2.3.2.2
TSEG ...................................................................................... 23
2.3.2.3
Protected Memory Range (PMR) – (programmable) ....................... 23
2.3.2.4
DRAM Protected Range (DPR) ..................................................... 24
2.3.2.5
Pre-allocated Memory................................................................ 24
2.3.2.6
Graphics Stolen Spaces ............................................................. 24
Intel
®
Management Engine (Intel
®
ME) UMA ................................ 25
2.3.2.7
2.3.3
PCI Memory Address Range (TOLUD – 4 GB)........................................... 25
2.3.3.1
APIC Configuration Space (FEC0_0000h – FECF_FFFFh) ................. 26
2.3.3.2
HSEG (FEDA_0000h – FEDB_FFFFh) ............................................ 27
2.3.3.3
MSI Interrupt Memory Space (FEE0_0000 – FEEF_FFFF) ................ 27
2.3.3.4
High BIOS Area ........................................................................ 27
2.3.4
Main Memory Address Space (4 GB to TOUUD)........................................ 27
2.3.4.1
Memory Re-claim Background .................................................... 28
2.3.4.2
Indirect Accesses to MCHBAR Registers........................................ 29
2.3.4.3
Memory Remapping .................................................................. 29
2.3.4.4
Hardware Remap Algorithm........................................................ 29
2.3.4.5
Programming Model .................................................................. 30
2.3.5
PCI Express* Configuration Address Space ............................................. 35
2.3.6
PCI Express* Graphics Attach (PEG) ...................................................... 35
2.3.7
Graphics Memory Address Ranges ......................................................... 36
2.3.7.1
IOBAR Mapped Access to Device 2 MMIO Space ............................ 36
2.3.7.2
Trusted Graphics Ranges ........................................................... 36
2.3.8
System Management Mode (SMM) ......................................................... 37
2.3.9
SMM and VGA Access through GTT TLB .................................................. 37
2.3.10
ME Stolen Memory Accesses ................................................................. 37
2.3.11
I/O Address Space .............................................................................. 38
2.3.11.1 PCI Express* I/O Address Mapping.............................................. 38
2.3.12
MCTP and KVM Flows ........................................................................... 39
2.3.13
Decode Rules and Cross-Bridge Address Mapping .................................... 39
2.3.13.1 DMI Interface Decode Rules ....................................................... 39
2.3.13.2 PCI Express* Interface Decode Rules........................................... 42
2.3.13.3 Legacy VGA and I/O Range Decode Rules..................................... 43
2.4
I/O Mapped Registers ........................................................................................ 46
2.5
PCI Device 0 Function 0 Configuration Space Registers........................................... 47
2.5.1
VID—Vendor Identification Register ....................................................... 48
2.5.2
DID—Device Identification Register........................................................ 49
2.5.3
PCICMD—PCI Command Register .......................................................... 49
2.5.4
PCISTS—PCI Status Register ................................................................ 50
2.5.5
RID—Revision Identification Register ..................................................... 52
2.5.6
CC—Class Code Register ...................................................................... 52
2.5.7
HDR—Header Type Register.................................................................. 53
2.5.8
SVID—Subsystem Vendor Identification Register ..................................... 53
2.5.9
SID—Subsystem Identification Register.................................................. 53
Datasheet, Volume 2
3
 2.5.10
CAPPTR—Capabilities Pointer Register ....................................................54
2.5.11
PXPEPBAR—PCI Express* Egress Port Base Address Register .....................54
2.5.12
MCHBAR—Host Memory Mapped Register Range Base Register ..................55
2.5.13
GGC—GMCH Graphics Control Register ...................................................55
2.5.14
DEVEN—Device Enable Register.............................................................57
2.5.15
PAVPC—Protected Audio Video Path Control Register ................................59
2.5.16
DPR—DMA Protected Range Register ......................................................59
2.5.17
PCIEXBAR—PCI Express* Register Range Base Address Register ................60
2.5.18
DMIBAR—Root Complex Register Range Base Address Register..................62
MESEG_BASE—Intel
®
Management Engine Base Address Register..............63
2.5.19
MESEG_MASK—Intel
®
Management Engine Limit Address Register.............64
2.5.20
2.5.21
PAM0—Programmable Attribute Map 0 Register .......................................65
2.5.22
PAM1—Programmable Attribute Map 1 Register .......................................66
2.5.23
PAM2—Programmable Attribute Map 2 Register .......................................67
2.5.24
PAM3—Programmable Attribute Map 3 Register .......................................68
2.5.25
PAM4—Programmable Attribute Map 4 Register .......................................69
2.5.26
PAM5—Programmable Attribute Map 5 Register .......................................70
2.5.27
PAM6—Programmable Attribute Map 6 Register .......................................71
2.5.28
LAC—Legacy Access Control Register......................................................72
2.5.29
REMAPBASE—Remap Base Address Register............................................76
2.5.30
REMAPLIMIT—Remap Limit Address Register ...........................................77
2.5.31
TOM—Top of Memory Register...............................................................77
2.5.32
TOUUD—Top of Upper Usable DRAM Register ..........................................78
2.5.33
BDSM—Base Data of Stolen Memory Register ..........................................79
2.5.34
BGSM—Base of GTT Stolen Memory Register ...........................................79
2.5.35
TSEGMB—TSEG Memory Base Register ...................................................80
2.5.36
TOLUD—Top of Low Usable DRAM Register..............................................80
2.5.37
SKPD—Scratchpad Data Register ...........................................................81
2.5.38
CAPID0_A—Capabilities A Register .........................................................82
2.5.39
CAPID0_B—Capabilities B Register .........................................................84
2.6
PCI Device 1 Function 0–2 Configuration Space Registers........................................86
2.6.1
VID—Vendor Identification Register........................................................87
2.6.2
DID—Device Identification Register ........................................................88
2.6.3
PCICMD—PCI Command Register ...........................................................88
2.6.4
PCISTS—PCI Status Register .................................................................90
2.6.5
RID—Revision Identification Register ......................................................92
2.6.6
CC—Class Code Register.......................................................................92
2.6.7
CL—Cache Line Size Register.................................................................92
2.6.8
HDR—Header Type Register ..................................................................93
2.6.9
PBUSN—Primary Bus Number Register ...................................................93
2.6.10
SBUSN—Secondary Bus Number Register ...............................................93
2.6.11
SUBUSN—Subordinate Bus Number Register ...........................................94
2.6.12
IOBASE—I/O Base Address Register .......................................................95
2.6.13
IOLIMIT—I/O Limit Address Register ......................................................95
2.6.14
SSTS—Secondary Status Register ..........................................................96
2.6.15
MBASE—Memory Base Address Register .................................................97
2.6.16
MLIMIT—Memory Limit Address Register.................................................98
2.6.17
PMBASE—Prefetchable Memory Base Address Register..............................99
2.6.18
PMLIMIT—Prefetchable Memory Limit Address Register ........................... 100
2.6.19
PMBASEU—Prefetchable Memory Base Address Upper Register ................ 100
2.6.20
PMLIMITU—Prefetchable Memory Limit Address Upper Register................ 101
2.6.21
CAPPTR—Capabilities Pointer Register .................................................. 101
2.6.22
INTRLINE—Interrupt Line Register ....................................................... 102
2.6.23
INTRPIN—Interrupt Pin Register .......................................................... 102
2.6.24
BCTRL—Bridge Control Register ........................................................... 103
2.6.25
PM_CAPID—Power Management Capabilities Register ............................. 104
4
Datasheet, Volume 2
2.6.26
PM_CS—Power Management Control/Status Register ............................. 105
2.6.27
SS_CAPID—Subsystem ID and Vendor ID Capabilities Register................ 107
2.6.28
SS—Subsystem ID and Subsystem Vendor ID Register........................... 107
2.6.29
MSI_CAPID—Message Signaled Interrupts Capability ID Register ............. 108
2.6.30
MC—Message Control Register ............................................................ 109
2.6.31
MA—Message Address Register ........................................................... 110
2.6.32
MD—Message Data Register ............................................................... 110
2.6.33
PEG_CAPL—PCI Express-G Capability List Register................................. 110
2.6.34
PEG_CAP—PCI Express-G Capabilities Register ...................................... 111
2.6.35
DCAP—Device Capabilities Register...................................................... 111
2.6.36
DCTL—Device Control Register............................................................ 112
2.6.37
DSTS—Device Status Register............................................................. 113
2.6.38
LCAP—Link Capabilities Register.......................................................... 114
2.6.39
LCTL—Link Control Register ................................................................ 116
2.6.40
LSTS—Link Status Register................................................................. 118
2.6.41
SLOTCAP—Slot Capabilities Register .................................................... 119
2.6.42
SLOTCTL—Slot Control Register .......................................................... 121
2.6.43
SLOTSTS—Slot Status Register ........................................................... 123
2.6.44
RCTL—Root Control Register ............................................................... 125
2.6.45
RSTS—Root Status Register................................................................ 126
2.6.46
DCAP2—Device Capabilities 2 Register ................................................. 127
2.6.47
DCTL2—Device Control 2 Register ....................................................... 128
2.6.48
LCAP2—Link Capabilities 2 Register ..................................................... 129
2.6.49
LCTL2—Link Control 2 Register ........................................................... 129
2.6.50
LSTS2—Link Status 2 Register ............................................................ 131
2.7
PCI Device 1 Function 0–2 Extended Configuration Registers................................. 132
2.7.1
PVCCAP1—Port VC Capability Register 1 ............................................... 133
2.7.2
PVCCAP2—Port VC Capability Register 2 ............................................... 133
2.7.3
PVCCTL—Port VC Control Register ....................................................... 134
2.7.4
VC0RCAP—VC0 Resource Capability Register......................................... 135
2.7.5
VC0RCTL—VC0 Resource Control Register............................................. 136
2.7.6
VC0RSTS—VC0 Resource Status Register ............................................. 137
2.7.7
PEG_TC—PCI Express* Completion Timeout Register ............................. 137
2.7.8
EQCTL0_1—Lane 0/1 Equalization Control Register ................................ 138
2.7.9
EQCTL2_3—Lane 2/3 Equalization Control Register ................................ 139
2.7.10
EQCTL4_5—Lane 4/5 Equalization Control Register ................................ 140
2.7.11
EQCTL6_7—Lane 6/7 Equalization Control Register ................................ 141
2.7.12
EQCTL8_9—Lane 8/9 Equalization Control Register ................................ 142
2.7.13
EQCTL10_11—Lane 10/11 Equalization Control Register ......................... 143
2.7.14
EQCTL12_13—Lane 12/13 Equalization Control Register ......................... 144
2.7.15
EQCTL14_15—Lane 14/15 Equalization Control Register ......................... 145
2.7.16
EQCFG—Equalization Configuration Register ......................................... 146
2.8
PCI Device 2 Configuration Space Registers ........................................................ 148
2.8.1
VID2—Vendor Identification Register ................................................... 149
2.8.2
DID2—Device Identification Register.................................................... 149
2.8.3
PCICMD2—PCI Command Register....................................................... 150
2.8.4
PCISTS2—PCI Status Register............................................................. 151
2.8.5
RID2—Revision Identification Register.................................................. 152
2.8.6
CC—Class Code Register .................................................................... 152
2.8.7
CLS—Cache Line Size Register ............................................................ 153
2.8.8
MLT2—Master Latency Timer Register .................................................. 153
2.8.9
HDR2—Header Type Register .............................................................. 153
2.8.10
GTTMMADR—Graphics Translation Table, Memory
Mapped Range Address Register.......................................................... 154
2.8.11
GMADR—Graphics Memory Range Address Register ............................... 155
2.8.12
IOBAR—I/O Base Address Register ...................................................... 156
Datasheet, Volume 2
5
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