3933, katalog

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3933
THREE-PHASE POWER
MOSFET CONTROLLER
GHC
5
29
SENSE
The A3933SEQ is a three-phase MOSFET controller for use with
bipolar brushless dc motors. It drives all n-channel external power
FETs, allowing system cost savings and minimizing
r
(DS)on
power loss.
The high-side drive block is implemented with bootstrap capacitors at
each output to provide the floating positive supply for the gate drive.
The high-side circuitry also employs a unique “intelligent” FET
monitoring circuit that ensures the gate voltages are at the proper levels
before turn-on and during the ON cycle. This device is targeted for
applications with motor supplies from 12 V to 28 V.
Internal fixed off-time PWM current-control circuitry can be used to
regulate the maximum load current to a desired value. The peak load-
current limit is set by the user’s selection of an input reference voltage
and external sensing resistor. The fixed off-time pulse duration is set
by a user-selected external RC timing network.
A power-loss braking circuit brakes the motor on an under-voltage
condition. The device is configured to either coast or dynamically
brake the motor when this occurs.
The A3933SEQ is supplied in a 32-lead rectangular (9 x 7) plastic
chip carrier (quad pack) for minimum-area, surface-mount applica-
tions.
CC
6
28
RC
GLB
7
27
PWM
SB
8
26
BRKSEL
GHB
9
25
BRKCAP
CB
10
24
BRAKE
GLA
11
23
DIR
SA
12
22
H2
GHA
13
21
H3
Dwg. PP-068
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
°
C
FEATURES
AND
BENEFITS
Drives External N-Channel FETs
Intelligent High-Side Gate Drive
Selectable Coast or Dynamic Brake on Power Down
Adjustable Dead Time for Cross-Conduction Protection
Selectable Fast or Slow Current-Decay Modes
Internal PWM Peak Current Control
Reset/Coast Input
120
Supply Voltage, V
BB
.............................
28 V
(peak) ..............................................
30 V
Terminal Voltage, V
CCOUT
.................
13.2 V
(peak) ..............................................
15 V
Logic Input Voltage Range,
V
IN
..................
-0.3 V to V
LCAP
+ 0.3 V
Sense Voltage Range,
V
SENSE
.............................
-5 V to V
LCAP
Output Voltage Range,
V
SA
, V
SB
, V
SC
..................
-5 V to +30 V
V
GHA
, V
GHB
, V
GHC
.
-5 V to V
BB
+ 14 V
V
CA
, V
CB
, V
CC
.....................
V
SX
+ 14 V
Operating Temperature Range,
T
A
.................................
-20
Hall Commutation with Internal Pullup
Internal 5-V Regulator
Low-Side Synchronous Rectification
Direction Control
PWM Speed-Control Input
Fault-Diagnostic Output
Under-Voltage Protection
°
C to +85
°
C
Junction Temperature, T
J
.................
+150
°
C
Storage Temperature Range,
T
S
...............................
-55
°
C to +150
°
C
19
°
3933
THREE-PHASE POWER
MOSFET CONTROLLER
Functional Block Diagram
+V
CONNECT FOR
12-V OPERATION
L
CAP
V
BB
V
CCOUT
REGULATOR
UNDER-
VOLTAGE
DETECT
BOOTSTRAP
MONITOR
BOOTSTRAP
CHARGE
C
X
H1
H2
H3
C
boot
TURN-ON
DELAY
HIGH-SIDE
DRIVER
GH
X
DIR
RESET
MODE
PWM
CONTROL
LOGIC
TO
1 OF 3
MOTOR
PHASES
GATE-SOURCE
MONITOR
S
X
1 OF 3 HIGH-SIDE DRIVERS
LOW-SIDE
SYNCHRONOUS
RECTIFICATION
DEAD-TIME
ADJUST
DEAD
TO
LCAP
RC
RC BLANKING
(FIXED OFF TIME)
R
T
C
T
REF
SENSE
+
–
TURN-ON
DELAY
LOW-SIDE
DRIVER
GL
X
TO
V
CCOUT
BRAKE
BRKSEL
1 OF 3 LOW-SIDE DRIVERS
BRAKE
PGND
R
S
BRKCAP
BOOTSTRAP LOW
V
GS
LOW
INVALID HALL
UNDERVOLTAGE
FAULT
AG
ND
TO
SENSE
Dwg. FP-045
RECOMMENDED OPERATING CONDITIONS
10%
Logic Input Voltage Range, V
IN
..............
-0.3 V to +4.8 V
Sense Voltage Range, V
SENSE
........................
-1 V to +1 V
RC Resistance ..........................................
10 k
±
Ω
PWM Frequency, f
PWM
.......................
20 kHz to 100 kHz
Ω
to 100 k
Dwg. OA-007-32
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1999, Allegro MicroSystems, Inc.
Supply Voltage, V
BB
......................................
15 V to 28 V
or, if V
BB
= V
CCOUT
...................................
12 V
3933
THREE-PHASE POWER
MOSFET CONTROLLER
ELECTRICAL SPECIFICATIONS at T
A
= 25
C, V
BB
= V
CCOUT
= 12 V, C
load
= 1000 pF, C
boot
= 0.047
µ
F
(unless noted otherwise).
Limits
Parameter
Symbol Conditions
Min Typ Max Units
Supply Current
Quiescent Current
I
BB
RESET low, f
PWM
= 40 kHz
– 16 19 mA
RESET high
– 15 17 mA
Reference Voltage
V
LCAP
4.75 5.0 5.25 V
Ref. Volt. Load Regulation
∆
V
LCAP(
∆
ILCAP)
I
LCAP
= 0 to -2 mA
– 10 25 mV
Output Voltage
V
CCOUT
V
BB
= 28 V
10.8 12 13.2 V
Output Voltage Regulation
∆
V
CCOUT(
∆
ICCOUT)
V
BB
= 28 V, I
CCOUT
= 0 to -10 mA
– – 25 mV
Digital Logic Levels
Logic Input Voltage
V
IH
2.0 – –
V
V
IL
– – 0.8 V
Logic Input Current
I
IH
V
IH
= 2 V
– <1.0 10
µ
A
I
IL
V
IL
= 0.8 V
-70 – -130
µ
A
Gate Drive
Low-Side Output Voltage
V
GLxH
9.5 10.5 11.5 V
V
GLxL
I
GLx
= 1 mA
– – 0.30 V
High-Side Output Voltage
V
GHxH
9.0 10.5 11.5 V
V
GHxL
I
GHx
= 1 mA
– – 0.25 V
Low-Side Output
t
rGLx
1 V to 8 V
– 50 –
ns
Switching Time
t
fGLx
8 V to 1 V
– 40 –
ns
High-Side Output
t
rGHx
1 V to 8 V
– 100 –
ns
Switching Time
t
fGHx
8 V to 1 V
– 100 –
ns
DEAD Time
t
DEAD
I
DEAD
= 10
µ
A
– 3000 –
ns
(Source OFF to Sink ON)
I
DEAD
= 215
µ
A
– 180 –
ns
Continued —
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
www.allegromicro.com
°
3933
THREE-PHASE POWER
MOSFET CONTROLLER
ELECTRICAL SPECIFICATIONS at T
A
= 25
C, V
BB
= V
CCOUT
= 12 V, C
load
= 0.001
µ
F, C
boot
= 0.047
µ
(unless noted otherwise), continued.
Limits
Parameter
Symbol Conditions
Min Typ Max Units
Bootstrap Capacitor
Bootstrap Charge Current
I
Cx
50 100 150 mA
Bootstrap Output Voltage
V
Cx
Reference Sx
9.5 10.5 11.5 V
Leakage Current
I
Cx
High side switched high, Sx = V
BB
– 15 20
µ
A
Current Limit
Offset Voltage
V
io
– 0
±
5.0 mV
Input bias current
I
SENSE
– – -1.0
µ
A
RC Charge Current
I
RC
850 945 1040
µ
A
RC Voltage Threshold
V
RCL
1.0 1.1 1.2 V
V
RCH
2.7 3.0 3.2 V
PWM frequency Range
f
PWM
Operating
20 – 100 kHz
Protection Circuitry
Undervoltage Threshold
UVLO Increasing V
BB
9.7 10.2 10.7 V
Decreasing V
BB
9.35 – 10.35 V
Boot-Strap Capacitor Volt.
V
CxSx
V
BB
= 12 V
9.5 – –
V
High-Side Gate-Source Volt. V
GHxSx
– 6.3 –
V
Fault Output Voltage
V
FAULT
I
O
= 1 mA
– – 0.8 V
Brake Function
Brake Cap. Supply Current
I
BRKCAP
V
BB
= 8 V, BRKSEL
≥
2 V
– 30 –
µ
A
Low-Side Gate Voltage
V
GLxH
V
BB
= 0, BRKCAP = 8 V
– 6.6 –
V
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
°
F
3933
THREE-PHASE POWER
MOSFET CONTROLLER
Terminal Descriptions
Terminal Name
1
PGND
RESET
— A logic input used to enable the device, internally
pulled up to V
LCAP
(+5 V). A logic HIGH will disable the
device and force all gate drivers to 0 V, coasting the motor. A
logic LOW allows the gate drive to follow commutation logic.
This input overrides BRAKE.
2
RESET
3
GLC
4
SC
GLA/GLB/GLC
— Low-side, gate-drive outputs for external
NMOS drivers. External series-gate resistors (as close as
possible to the NMOS gate) can be used to control the slew rate
seen at the power-driver gate, thereby controlling the di/dt and
dv/dt of the SA/SB/SC outputs. Each output is designed and
specified to drive a 1000 pF load with a rise time of 50 ns.
5
GHC
6
CC
7
GLB
8
SB
9
GHB
SA/SB/SC
— Directly connected to the motor, these terminals
sense the voltages switched across the load. These terminals
are also connected to the negative side of the bootstrap capaci-
tors and are the negative supply connections for the floating
high-side drive.
10
CB
11
GLA
12
SA
13
GHA
14
CA
GHA/GHB/GHC
— High-side, gate-drive outputs for external
NMOS drivers. External series-gate resistors (as close as
possible to the NMOS gate) can be used to control the slew rate
seen at the power-driver gate, thereby controlling the di/dt and
dv/dt of the SA/SB/SC outputs. Each output is designed and
specified to drive a 1000 pF load with a rise time of 100 ns.
15
V
CCOUT
16
LCAP
17
FAULT
18
MODE
19
V
BB
CA/CB/CC
— High-side connections for the bootstrap capaci-
tors, positive supply for high-side gate drive. The bootstrap
capacitor is charged to approximately V
CCOUT
when the
associated output SA/SB/SC terminal is low. When the output
swings high, the voltage on this terminal rises with the output to
provide the boosted gate voltage needed for n-channel power
FETs.
20
H1
21
H3
22
H2
23
DIR
24
BRAKE
25
BRKCAP
26
BRKSEL
continued next page
27
PWM
28
RC
29
SENSE
30
REF
31
DEAD
32
AGND
www.allegromicro.com
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