4017, Noty katalogowe
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
·
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
·
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4017B
MSI
5-stage Johnson counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
5-stage Johnson counter
HEF4017B
MSI
DESCRIPTION
A HIG
H
on MR resets the counter to zero
(O
o
= O
5-9
= HIGH
; O
1
to O
9
= LOW) independent of the
clock inputs (CP
0
, CP
1
).
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
The HEF4017B is a 5-stage Johnson decade counter with
ten spike-free decoded active HIGH outputs (O
o
to O
9
)
, an
active LOW output from the most significant flip-fl
op
(O
5-9
),
active HIGH and active LOW clock inputs (CP
0
, CP
1
) and
an overriding asynchronous master reset input (MR).
The counter is advanc
ed b
y either a LOW to HIGH
transition at
CP
0
while CP
1
is LOW or a HIGH to LOW
transition at CP
1
while CP
0
is HIGH (see also function
table).
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
When cascading counters, the O
5-9
output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP
0
input of the next counter.
Fig.1 Functional diagram.
PINNING
CP
0
clock input (LOW to HIGH triggered)
CP
1
clock input (HIGH to LOW triggered)
MR
master reset input
O
0
to O
9
decoded outputs
O
5-9
carry output (active LOW)
Fig.2 Pinning diagram.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
HEF4017BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4017BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4017BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
January 1995
2
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Fig.3 Logic diagram.
Philips Semiconductors
Product specification
5-stage Johnson counter
HEF4017B
MSI
FUNCTION TABLE
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
MR
CP
0
CP
1
OPERATION
H
X
X
O
0
= O
5-9
= H; O
1
to O
9
=L
L
H
Counter advances
4.
= positive-going transition
L
L
Counter advances
5.
= negative-going transition
L
L
X
No change
L
X
H
No change
L
H
No change
L
L
No change
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25
°
C; C
L
= 50 pF; input transition times
£
20 ns
V
DD
V
SYMBOL MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagati
on
delays
CP
0
, CP
1
®
O
0
to O
9
5
140
280
ns
113 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
55
110
ns
44 ns
+
(0,23 ns/pF) C
L
15
40
80
ns
32 ns
+
(0,16 ns/pF) C
L
5
125
250
ns
98 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
50
100
ns
39 ns
+
(0,23 ns/pF) C
L
15
40
80
ns
32 ns
+
(0,16 ns/pF) C
L
CP
0
, CP
1
®
O
5-9
5
145
290
ns
118 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
55
110
ns
44 ns
+
(0,23 ns/pF) C
L
15
40
80
ns
32 ns
+
(0,16 ns/pF) C
L
5
125
250
ns
98 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
50
100
ns
39 ns
+
(0,23 ns/pF) C
L
15
40
80
ns
32 ns
+
(0,16 ns/pF) C
L
MR
®
O
1
to O
9
5
115
230
ns
88 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
50
100
ns
39 ns
+
(0,23 ns/pF) C
L
15
35
70
ns
27 ns
+
(0,16 ns/pF) C
L
MR
®
O
5-9
5
110
220
ns
83 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
45
90
ns
34 ns
+
(0,23 ns/pF) C
L
15
35
70
ns
27 ns
+
(0,16 ns/pF) C
L
MR
®
O
0
5
130
260
ns
103 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
55
105
ns
44 ns
+
(0,23 ns/pF) C
L
15
40
75
ns
32 ns
+
(0,16 ns/pF) C
L
January 1995
4
Philips Semiconductors
Product specification
5-stage Johnson counter
HEF4017B
MSI
V
DD
V
SYMBOL MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Output transition
times
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
HIGH to LOW
10
t
THL
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
LOW to HIGH
10
t
TLH
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25
°
C; C
L
= 50 pF; input transition times
£
20 ns
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
Hold times
5
90
45
ns
CP
0
®
CP
1
10
t
hold
40
20
ns
15
20
10
ns
5
80
40
ns
CP
1
®
CP
0
10
t
hold
40
20
ns
15
30
10
ns
Minimum clock
pulse width:
5
80
40
ns
t
WCPL
=
t
WCPH
CP
0
= LOW;
10
40
20
ns
see also waveforms
CP
1
= HIGH
15
30
15
ns
Figs 4 and 5
Minimum MR
5
50
25
ns
pulse width; HIGH
10
t
WMRH
30
15
ns
15
20
10
ns
Recovery time
5
60
30
ns
for MR
10
t
RMR
30
15
ns
15
20
10
ns
Maximum clock
5
6
12
MHz
pulse frequency
10
f
max
12
24
MHz
15
15
30
MHz
V
DD
V
TYPICAL FORMULA FOR P (
m
W)
Dynamic power
5
500 f
i
+å
(f
o
C
L
)
´
V
DD
2
where
dissipation per
10
2200 f
i
+å
(f
o
C
L
)
´
V
DD
2
f
i
= input freq. (MHz)
package (P)
15
6000 f
i
+å
(f
o
C
L
)
´
V
DD
2
f
o
= output freq. (MHz)
C
L
= load cap. (pF)
å
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
5
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