3965, katalog

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3965
PRELIMINARY DATASHEET - 12/4/2002
(Subject to change without notice)
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
ABSOLUTE MAXIMUM RATINGS
at T
A
= +25
°
C
Load Supply Voltage, VBB ..........................
20 V
Output Current, I
OUT
............................ ±
500 mA*
Logic Supply Voltage, V
DD
..........................
7.0 V
Logic Input Voltage Range,
V
IN
......................
-0.3 V to V
DD
+ 0.3 V
(t
W
<30ns) ..................
-1.0V to V
DD
+1V
Sense Voltage, V
SENSE
..................................
0.5 V
Reference Voltage, V
REF
.................................
3 V
Package Power Dissipation (T
A
= +25°C), P
D
A3965SLB...........................
50
°
C/W**
Designed for Pulse Width Modulated (PWM) current control of low
voltage stepper motors, the A3965S is capable of output currents to ± 500 mA
and operating voltages to 20 V.
The A3965 is particularly attractive for low power or battery
operated motors where minimal power consumption is desired. A SLEEP
mode disables all circuitry and typically draws less than 1µA supply current
from motor and logic supply. During operation the fixed frequency ON
pulses of each H-bridge are 180 degrees out of phase to minimize the peak
demand required of the motor supply allowing savings in size and cost of
external power supply components.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a stepper motor with externally applied
PWM control signals.
Operating Temperature Range,
T
A
................................
-20
°
C to +85
°
C
Junction Temperature, T
J
.........................
+150
°
C
Storage Temperature Range,
T
S
...............................
-55
°
C to +150
°
C
*
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any set of
conditions, do not exceed the specified current rating or a
junction temperature of 150°C.
*Measured with 062" thick FR4, two sided PCB with 1 sq
inch copper area.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of V
DD
and charge pump, and crossover
current protection. Special power up sequencing is not required.
The A3965 is supplied in a 24-lead plastic SOIC with a copper
batwing tab (suffix ‘LB’).
FEATURES
±500 mA, 20 V Output Rating
2.85 to 5.5V Logic Supply Operation
Sleep Mode for Minimum Power Consumption
Fixed Frequency PWM
Offset On Pulses to Minimize Peak Supply Transient Currents
Internal UVLO and Thermal Shutdown Circuitry
Crossover-Current Protection
1
3965 DMOS Dual Full Bridge
PWM Motor Driver
Functional Block Diagram
.22uf
V
DD
UVLO AND
FAULT
DETECT
REGULATOR
CHARGE PUMP
V
CP
BANDGAP
V
BB
DMOS H-BRIDGE
V
CP
OUT
1A
SLEEP
OUT
1B
PHASE2
PHASE1
CONTROL
LOGIC
SENSE1
ENABLE1
ENABLE2
GATE
DRIVE
DMOS H-BRIDGE
V
BB
OSC
OUT
2A
RC
OUT
2B
S
Q
SENSE2
R
REF2
1/6
S
Q
SENSE1
R
SENSE2
REF1
1/6
GROUND
2
3965 DMOS Dual Full Bridge
PWM Motor Driver
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
BB
= 20 V, V
DD
= 3.0 V, V
SENSE
= 0.5 V, f
PWM
< 50KHz (unless
noted otherwise)
Limits
Characteristics
Symbol
Test Conditions
Min.
Typ. Max.
Units
Output Drivers
Load Supply Voltage Range
VBB
Operating, I
OUT
=
±
500 mA
6
–
20
V
During Sleep Mode
0
20
V
Output Leakage Current
I
DSS
V
OUT
= V
BB
–
<1.0
20
µA
V
OUT
= 0 V
–
<–1.0
-20
µ
A
Output On Resistance
R
DSON
Source Driver, I
OUT
= -500 mA
–
1.2
1.35
Ω
Sink Driver, I
OUT
= 500 mA
–
.75
.9
Ω
Source Driver, I
OUT
= -500 mA; VBB=6V
1.3
1.5
Ω
Sink Driver, I
OUT
= 500 mA, VBB=6V
.85
1.0
Ω
Body Diode Forward Voltage
V
F
Source Diode, I
F
= -500 mA
–
1
–
V
Sink Diode, I
F
= 500mA
–
1
–
V
Motor Supply Current
I
BB
f
PWM
< 50 kHz
–
3.5
7
mA
Charge Pump On, Outputs Disabled
–
1.5
3
mA
Sleep Mode
–
–
10
uA
Logic Supply Current
I
DD
f
PWM
< 50 kHz
4.5
mA
Outputs Off
3.6
mA
Sleep Mode (Inputs below .5V)
<1
10
µ
A
Control Logic
Logic Supply Voltage Range
V
DD
Operating
2.85
5.5
V
Logic Input Voltage
V
IN(1)
V
DD
*.7
–
V
V
IN(0)
–
V
DD
*.3
V
Logic Input Current
I
IN(1)
V
IN
= V
DD
*.7
-20
<1.0
20
µA
I
IN(0)
V
IN
= V
DD
*.3
-20
<1.0
20
µA
3
3965 DMOS Dual Full Bridge
PWM Motor Driver
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
BB
= 20V, V
DD
= 3.0 V, V
SENSE
= 0.5 V (unless noted otherwise)
Limits
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max. Units
Control Logic
Reference Input Current
I
REF
V
REF
= V
DD
-1
0
1
µ
A
VREF input voltage range
V
REF
0
V
DD
- .1
Reference Divider Ratio
V
REF
/V
S
6
G
M
Error
V
ERR
V
REF
= 1.5V
-5
5
%
(Note 3)
V
REF
= .5V
-10
10
%
Propagation Delay
t
PD
PWM CHANGE TO SOURCE OFF
–
150
–
ns
PWM CHANGE TO SINK OFF
–
150
–
ns
PWM CHANGE TO SOURCE ON
–
1000
–
ns
PWM CHANGE TO SINK ON
–
1000
–
ns
DISABLE TO SOURCE ON
–
200
–
ns
DISABLE TO SINK ON
–
200
–
ns
t
COD
300
850
1200
ns
PWM RC Frequency
f
OSC
R = 1000pf, C = 20K
47.4
Khz
Blank Time
t
BLANK
R = 1000pf, C = 20K
.8
1.21
1.6
µ
s
Thermal Shutdown Temp.
T
J
–
165
°C
Thermal Shutdown Hysteresis
∆
T
J
–
15
–
°C
UVLO Enable Threshold
Rising V
DD
2.5
2.8
V
UVLO Hysteresis
0.05
0.10
–
V
NOTES: 1. Typical Data is for design information only.
2.
Negative current is defined as coming out of (sourcing) the specified device pin.
3.
V
ERR
=((V
REF
/6) – V
SENSE
)/(V
REF
/6)
4
3965 DMOS Dual Full Bridge
PWM Motor Driver
Functional Description
Sleep Mode.
The input pin SLEEP is dedicated to put the
device into a minimum current draw mode. All circuits are
disabled including the VDD undervoltage monitor.
Fixed Frequency PWM.
Selection of an external RC
sets the oscillator frequency as follows:
f
OSC
= 1/ ( 850ns + t
BLANK
+R
T
C
T
))
Blank Time.
When a source driver turns on, a current
spike occurs due to the reverse recovery currents of the
clamp diodes and/or switching transients related to
distributed capacitance in the load. To prevent this current
spike from erroneously resetting the source enable latch, the
sense comparator is blanked. The blank duration is
determined by the time it takes to charge the external RC
.38*V
DD
volts with a 1mA current source.
t
BLANK
= C
T
*.38*V
DD
/ ( 1mA – ( .41*V
DD
/R
T
))
Shutdown.
In the event of a fault due to excessive
junction temperature, or low voltage on V
CP
or V
REG
, the
outputs of the device are disabled until the fault condition is
removed. At power up, and in the event of low V
DD
, the
UVLO circuit disables the drivers
Current Regulation.
Load current is regulated by a
fixed frequency PWM control circuit. When the outputs of
the DMOS H-bridge are turned on, current increases in the
motor winding until it reaches a value given by:
I
TRIP
= V
REF
/(6*R
SENSE
)
VREG.
This supply voltage is used to run the sink side
DMOS outputs. VREG is internally monitored and in the
case of a fault condition, the outputs of the device are
disabled. The VREG pin should be decoupled with a 0.22
µF capacitor to ground.
At the trip point, the sense comparator resets the source
enable latch, turning off the source. At this point, load
inductance causes the current to recirculate until the end
fixed frequency cycle. (see timing diagram)
VREF.
The V
REF
voltage is divided down by 6 and
compared to the voltage across the sense resistor to set the
value of bridge current that will trip the PWM comparator.
The V
REF
input is a high impedance input and can be
connected to V
DD
, if desired, as well as via resistor divider.
Note: When connected to V
DD
, the V
BB
voltage must be 1.8V
greater than V
DD
to allow proper headroom for the buffer
output.
Charge Pump.
The Charge Pump is used to generate a
supply above VBB
to drive the source side DMOS gates. A
0.22 uF ceramic monolithic capacitor should be connected
between CP
1
and CP
2
for pumping purposes. A 0.22 uF
ceramic monolithic capacitor should be connected between
V
CP
and VBB to act as a reservoir to run the high side
DMOS devices. The V
CP
Voltage is internally monitored and
in the case of a fault condition the outputs of the device are
disabled.
Thermal protection
. Circuitry turns OFF all drivers
when the junction temperature reaches 165°C typically. It is
intended only to protect the device from failures due to
excessive junction temperatures and should not imply that
output short circuits are permitted. Thermal shutdown has a
hysteresis of approximately 15°C.
5
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