3971, katalog

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3971
ADVANCE INFORMATION
(Subject to change without notice)
May 2, 2000
DUAL DMOS
FULL-BRIDGE DRIVER
NO
CONNECTION
LOGIC
GROUND
S
10
1
NC
V
DD
24
LOGIC
SUPPLY
Designed to interface between external PWM control logic and
inductive loads such as relays, solenoids, dc motors, or stepper motors,
each full bridge can operate with output currents to
2.5 A and operating
voltages to 50 V.
2
23
PWM
2
3
22
S
20
Low r
DS(on)
DMOS output drivers provide low power dissipation
during PWM operation. Internal charge pump circuitry is used to create
a boosted voltage to fully enhance the high-side DMOS switches.
OUT
1A
4
21
OUT
2A
LOAD
SUPPLY
1
5
V
BB1
V
BB2
20
LOAD
SUPPLY
2
GROUND
6
19
GROUND
Three TTL-compatible logic-input terminals per bridge allow flex-
ibility in configuring PWM control.
GROUND
7
18
GROUND
SENSE
1
8
17
SENSE
2
Internal circuit protection includes thermal shutdown with hysteresis,
and crossover-current protection. Special power -up sequencing is not
required.
OUT
1B
9
16
OUT
2B
S
11
10
15
S
21
PWM
1
11
14
V
CP
The A3971SLB is supplied in a 24-lead plastic SOIC with a copper
batwing tab. The power tab is at ground potential and needs no electri-
cal isolation.
CP1
12
CHARGE PUMP
13
CP2
Dwg. PP-069-2
C
Load Supply Voltage, V
BB
................
50 V
Output Current, I
OUT
Transient (<500 ns) ...................
5 A
2.5 A Load Current Capability per Bridge
Logic Supply Voltage,
V
DD
............................................
7.0 V
Sense Voltage, V
SENSE
......................
0.5 V
Logic Input Voltage Range,
V
IN
..................
-0.3 V to V
DD
+ 0.3 V
High-Side Gate Voltage ...........
V
BB
+ 8 V
Package Power Dissipation,
P
D
.............................................
2.2 W
Operating Temperature Range,
T
A
.............................
-20
°
C to +85
°
C
Junction Temperature, T
J
.............
+150
°
C
Storage Temperature Range,
T
S
...........................
-55
°
C to +150
°
C
Parallel Outputs for 5 A Load-Current Capability
Low r
DS(on)
Outputs
Typically 325 m
source, 175 m
sink
Synchronous Rectification via Control Logic
Internal Undervoltage Monitor
Crossover-Current Protection
Source Connections for External Current Sensing
Thermal Shutdown Circuitry
Output duty cycle, ambient temperature, and
heat sinking may limit current rating. Under
any set of conditions, do not exceed the
specified current rating or a junction tempera-
ture of 150
C.
Always order by complete part number:
A3971SLB
.
9
ABSOLUTE MAXIMUM RATINGS
at T
A
= +25
FEATURES
±
 3971
DUAL DMOS
FULL-BRIDGE DRIVER
FUNCTIONAL BLOCK DIAGRAM
0.22
µ
F/100 V
LOGIC
SUPPLY
13
CP2
12
CP1
LOAD
SUPPLY
V
DD
V
REF
LOW SIDE
SUP
PLY
V
CP
24
14
0.22
µ
F
VOLTAGE
REFERENCE
CHARGE
PUMP
50 V
20
V
BB2
V
CP
DMOS H-BRIDGE
UVLO &
THERMAL
SHUTDOWN
21
OUT
2A
16
OUT
2B
S
10
3
BRIDGE 1
CONTROL
LOGIC
S
11
10
SENSE
2
,
(OPTIONAL)
C
S
17
PWM
1
11
GATE
DRIVE
DMOS H-BRIDGE
5
V
BB1
S
20
22
BRIDGE 2
CONTROL
LOGIC
S
21
15
4
OUT
1A
PWM
2
23
OUT
1B
9
,
(OPTIONAL)
LGND
SENSE
1
2
8
GROUND
6 7
18 19
Dwg. FP-050
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, 2002 Allegro MicroSystems, Inc.
R
S
R
S
C
S
3971
DUAL DMOS
FULL-BRIDGE DRIVER
ELECTRICAL CHARACTERISTICS at T
A
= +25
C, V
BB
= 50 V, V
DD
= 5.0 V (unless otherwise noted).
Limits
Characteristic
Symbol Test Conditions
Min. Typ. Max. Units
Load Supply Voltage Range
V
BB
Operating
10
—
50
V
Logic Supply Voltage Range
V
DD
Operating
4.5
5.0
5.5
V
Load Supply Current
I
BB
Operating, each supply, no load
—
—
3.0
mA
Logic Supply Current
I
DD
Operating
—
—
5.0
mA
Output Drivers
Output Leakage Current
I
DSS
V
OUT
= V
BB
—
<1.0
20
A
V
OUT
= 0 V
—
<-1.0
-20
mA
Output ON Resistance
r
DS(on)
High-side switch, I
OUT
= -2.5 A
—
325
375
m
Low-side switch, I
OUT
= 2.5 A
—
175
200
m
Body Diode Forward Voltage
V
F
Source diode, I
F
= 2.5 A
—
1.2
—
V
Sink diode, I
F
= 2.5 A
—
1.0
—
V
High-Side Gate Voltage
V
CP
C = 0.22
F, reference V
BB
6.0
6.5
7.0
V
Control Logic
Logic Input Voltage
V
IN(0)
—
—
0.8
V
V
IN(1)
2.0
—
—
V
Logic Input Current
I
IN(0)
V
IN
= 0 V
—
<1.0
-5.0
A
I
IN(1)
V
IN
= 5.0 V
—
20
50
A
Propagation Delay Time
t
PD
50% to 90%:
PWM change to source off
—
50
—
ns
PWM change to sink off
—
60
—
ns
PWM change to source on
—
565
—
ns
PWM change to sink on
—
665
—
ns
Disable to source on
—
150
—
ns
Disable to sink on
—
250
—
ns
Thermal Shutdown Temperature
T
J
—
165
—
C
Thermal Shutdown Hysteresis
T
J
—15
—
C
UVLO Threshold
V
UVLO
Increasing V
DD
3.9
4.15
4.4
V
UVLO Hysteresis
V
UVLO
—
0.15
—
V
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
www.allegromicro.com
3971
DUAL DMOS
FULL-BRIDGE DRIVER
Logic Truth Table
PWM
x
S
x0
S
x1
OUT
xA
OUT
xB
Function
X
0
0
Z
Z
Disable
0
0
1
L
H
Forward
0
1
0
H
L
Reverse
0
1
1
L
L
Synchronous
1
0
1
L
L
Rectification/
1
1
1
L
L
Slow Decay
1
1
0
L
L
Chop
Terminal List
Terminal Name
Description
1
NC
No (Internal) connection
2
LGND
Logic ground
3
S
10
Control input, bridge 1
4
OUT
1A
Output A, bridge 1
5
V
BB1
Load supply voltage, bridge 1
6, 7
GND
Ground
8
SENSE
1
Sense resistor, bridge 1
9
OUT
1B
Output B, bridge 1
10
S
11
Control input, bridge 1
11
PWM
1
Control input, bridge 1
12
CP1
Charge-pump capacitor
13
CP2
Charge-pump capacitor
14
V
CP
Reservoir capacitor
15
S
21
Control input, bridge 2
16
OUT
2B
Output B, bridge 2
17
SENSE
2
Sense resistor, bridge 2
18, 19
GND
Ground
20
V
BB2
Load supply voltage, bridge 2
21
OUT
2A
Output A, bridge 2
22
S
20
Control input, bridge 2
23
PWM
2
Control input, bridge 2
24
V
DD
Logic supply voltage
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3971
DUAL DMOS
FULL-BRIDGE DRIVER
Functional Description
Charge Pump.
The DMOS output stage requires a
charge pump to bring the high-side gate-source voltage
approximately 8 V above the V
BB
supply. Two external
components are required, a pumping capacitor connected
between CP1 and CP2 and a reservoir capacitor connected
between V
BB
and V
CP
. Ceramic 0.22
F capacitors are
Layout.
The printed wiring board should use a heavy
ground plane. For optimum electrical and thermal perfor-
mance, the driver should be soldered directly onto the
board. If external current sensing is used, the ground side
of R
S
should have an individual path to the ground
terminal(s) of the device. This path should be as short as
is possible physically and should not have any other
components connected to it. The load supply terminal
should be decoupled with an electrolytic capacitor
( >47
recommended.
Control Logic.
Each bridge is controlled by three TTL-
compatible inputs. The inputs are resistively pulled to
ground (via 250 k
). A crossover-delay circuit protects
the outputs from a shoot-thru condition when going from a
forward or reverse on state to synchronous rectification/
slow decay chop (both sink drivers on). If the logic is in
the DISABLE state and changes to an on state the 415 ns
crossover delay does not occur.
Protection Circuitry.
In the event of a fault due to
excessive junction temperature, or low voltage on V
CP
or
V
DD
, the outputs of the device are disabled until the fault
condition is removed.
Current Sensing.
If external current-sensing circuitry
is used, the sense resistor should have an independent
ground return to the ground terminal of the device. Due to
current transients during switching, a 0.1
F is recommended) placed as close to the device as
is possible.
Parallel Operation.
For high-power applications, the
two DMOS full bridges in the A3971 may be connected in
parallel as shown below. The current will be shared
equally in each full bridge due to the positive temperature
coefficient of the DMOS
r
DS(on)
.
+5 V
1
NC
V
DD
24
2
23
F capacitor
should be connected from the sense terminal to the
batwing tab connection of the package. This capacitor
reduces voltage swings at the terminal due to the fast di/dt,
which in turn ensures that the sink driver gate-source
voltage stays within the safe operating area. Allegro
MicroSystems recommends a value of R
S
given by:
R
S
= 0.5/I
TRIP
max.
Thermal protection.
Circuitry turns off all drivers
when the junction temperature reaches 165
3
22
4
21
15–50 V
15–50 V
5
V
BB1
V
BB2
20
6
19
7
18
8
17
9
9
16
C, typically.
It is intended only to protect the device from failures due
to excessive junction temperatures and should not imply
that output short circuits are permitted. Thermal shut-
down has a hysteresis of approximately 15
10
15
11
14
12
CHARGE PUMP
13
C.
Dwg. EP-069
www.allegromicro.com
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